1. Field of the Invention
The present invention generally relates to a memory compiler, and more particularly to a memory compiler that takes into consideration of the speed, power and area with automatic optimization.
2. Description of Related Art
A memory compiler, such as a RAM (random-access memory) compiler, may be adapted to generate memory components or instances in an automatic manner. The memory compiler may be developed to preferably support system-on-chip (SoC) design capabilities. Conventional memory compilers, however, consider only one factor (for example, speed, power or density) to generate memory instances. As a result, the generated memory instances are mostly not optimized to client's requirements.
Moreover, in generating the memory instances, the conventional memory compilers operate in a device-level manner. As a result, it is very time-consuming to optimize the memory instances.
For these reasons, the conventional memory compilers could not effectively and rapidly generate the optimized memory instances. A need has thus arisen to propose a novel memory compiler to overcome the disadvantages of the conventional memory compilers.